Capacitors are commonly employed in digital and memory ICs for a variety of purposes, such as to store electrical charge, to block DC voltage levels, and to stabilize power supplies. In memory ICs, for example dynamic random access memories (DRAMs), a capacitor is used to hold enough charge to represent a detectable logic state.
Polysilicon is typically used to construct the plates of the capacitor. Polysilicon is not necessarily the optimum material to form the capacitor plates, because its doping characteristics result in variable capacitance in the polysilicon plate-polysilicon plate capacitor. In polysilicon capacitors the value of capacitance varies relative to the voltage level applied to the capacitor. The resistance of the polysilicon tends to be dependent on, and therefore a function of, the level of voltage applied to the polysilicon. Polysilicon capacitors are also frequently located in positions in the IC where the surrounding IC components degrade the performance of the capacitor. For example, locating the capacitor on the substrate increases the parasitic effect on the capacitor, further degrading its performance.
Despite these effects, the variance in capacitance is not of primary concern in memory ICs because the capacitor is required to accept charge, to hold some or all of the charge for a time period and then discharge, all in a reliable manner. Furthermore, since polysilicon is also used to fabricate other components of the IC, such as transistors and conductors, the plates of the capacitors can be formed simultaneously with the other components of the IC, thus simplifying the construction process and reducing fabrication costs.
In analog circuit applications, on the other hand, capacitors are frequently used as impedance elements whose response characteristic must be linear. If the impedance of the capacitor is not fixed and reliably ascertainable, the response of the capacitor will vary non-linearly. As a result, the performance of the analog circuit may be unsatisfactory.
The recent development of system level integrated circuits (SLICs) and application specific integrated circuits (ASICs) have combined linear or analog circuitry and digital circuitry on the same IC. In such applications, linear capacitors have become somewhat problematic. Polysilicon is not a desirable material from which to form linear capacitors because of its non-linear response characteristics. The fabrication technology for memory capacitors is not generally applicable for fabricating capacitors that may be required to serve as both digital components and analog components.
Capacitors also affect the cost of the IC. In general, the cost of the IC is directly related to the size or surface area of the substrate upon which the IC is constructed. If the IC components require a large amount of space, a larger substrate is required, and the IC cost increases.
The ongoing evolution of miniaturizing ICs has resulted in reduced costs and more circuit functionality for a given substrate size and manufacturing cost. For example, only a few years ago spacing between adjoining circuit elements in a typical IC was in the neighborhood of two to three microns. Today, many ICs are being designed at spacing distances as small as 0.35 microns or less. To accommodate narrower spacing, the electrical conductors are reduced in width. The reduction in width is compensated for by increasing the thickness of the conductors to avoid degrading the quality of the signal conducted. Metal conductors have also been substituted for polysilicon conductors, because the metal conductors provide better signal conducting capabilities.
Increasing the thickness of the conductors also requires increases in the thickness of the dielectric insulation material which separates and covers the conductors and components. The thickness of the dielectric must be greater than the height or topology difference among the components, to provide adequate insulation to separate the layers and components of the IC structure from one another. Increases in the thickness of the dielectric material are possible, in part, as a result of advanced planarization techniques such as chemical mechanical polishing (CMP). CMP smooths relatively significant variations in the height of the different components to a planar surface. Smoothing the variable-height topology to a planar surface allows the typical lithographic semiconductor fabrication techniques to be used to form considerably more layers than were previously possible in IC construction. Previously, only one or two layers were typically constructed before the topology variations created such significant depth of focus problems with lithographic processes that any further precision fabrication of layered elements was prevented. However, because of CMP, the number of layers of the IC is no longer limited by the topology. Some present ICs are formed by as many as five or more separate metal or interconnect layers, each of which is separated by a CMP planarized dielectric layer. Consequently, CMP has created the opportunity to incorporate more circuitry on a single substrate in a single IC.
It is with regard to these and other considerations that the present invention has evolved.